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arm64: Add explicit barrier after address translation instruction

Description

arm64: Add explicit barrier after address translation instruction

Following ARMARM sec D5.2.11, which says:

Where an instruction results in an update to a System register,
as is the case with the AT * address translation instructions,
explicit synchronization must be performed before the result is
guaranteed to be visible to subsequent direct reads of the
PAR_EL1.

Reviewed By: andrew
MFC after: 3 weeks
Sponsored by: Ampere Computing
Differential Revision: https://reviews.freebsd.org/D34665

(cherry picked from commit 7be7bd67758520ea2f9784a81ad244e99a7632f0)

Details

Provenance
scottphAuthored on Mar 25 2022, 4:04 PM
Reviewer
andrew
Differential Revision
D34665: arm64: Add explicit barrier after address translation instruction
Parents
rG2c013d142b14: arm64: pmap: Mask VA operand in TLBI instructions
Branches
Unknown
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