chroot into a 32-bit ARMv7 dist on a FreeBSD/arm64 system and run 'procstat -x' to verify that HWCAP/HWCAP2 are present in the aux array. Tested with qemu-aarch64 with cortexA53 and A72 cpu types, and also on AWS Graviton (backport to 13)
We should only read these if EL0 supports AArch32. The docs say direct access is unknown if no exception levels support AArch32, however I'm unsure if that means the values are unknown, or the hw could raise an exception.
This does raise the issue, btw, that 'cc -m32' probably doesn't work today on aarch64. For that to work, we'd need to merge the MD headers the way sys/x86/include works. However, we can tell people to setup a armv7 chroot and use --sysroot to point to that along with -m32 as a workaround. If we really care about freebsd32 on aarch64 we should figure out a solution for /usr/include/machine to support both eventually.
We decided a long time ago that we didn't care about that.
A few comments on register macro names & values.
I've also created D31201 to rework how we set the HWCAPS values. I'm happy to move the 32-bit HWCAPS to that format based on this change after the register and HWCAP32* macros have been committed.
We don't normally add _EL1 on these definitions
I've been following capitalisation from the documentation to help auto generate these registers so these would be ID_PFR0_State...
Maybe call this ID_PFR0_EL1_CSV2_HWCTX as later revisions of the architecture add a variant that branch targets trained on both different hardware contexts and different addresses can control speculative execution on different hardware contexts and addresses respectively.
Maybe MVFR1_SIMDHP_CONV (or _CONV_SP) and MVFR1_SIMDHP_ARITH so it's obvious the former only allows for conversion, while the latter adds arithmetic operations.
Maybe MVFR1_FPHP_CONV_SP and MVFR1_FPHP_CONV_DP and add MVFR1_FPHP_CONV_ARITH (UL(0x3)...) to indicate support for half-precision arithmetic operations.
- Remove HWCAP32_THUMBEE as this is unused in ARMv8
- Update COMPAT HWCAP comments to reflect ARMv8 usage.
- Print aarch32 regs, and compare across all CPUs.
- Remove _EL1 from register defines.
- Fix typo in ID_ISAR5_VCMA_IMPL constant.
- FPshVec -> FPShVec in register defines.
- Review feedback on register names
The register printing may be a bit verbose: feedback welcome.
AArch32 Instruction Set Attributes 5 = <CRC32,SHA2,SHA1,AES+VMULL> AArch32 Media and VFP Features 0 = <FPRound,FPSqrt,FPDivide,DP VFPv3+v4,SP VFPv3+v4,AdvSIMD> AArch32 Media and VFP Features 1 = <SIMDFMAC,FPHP DP Conv,SIMDHP SP Conv,SIMDSP,SIMDInt,SIMDLS,FPDNaN,FPFtZ>
The case of no EL0 32-bit should work, though untested.
Tested on a M1 Mac under Parallels:
AArch32 Instruction Set Attributes 5 = <SEVL Nop> AArch32 Media and VFP Features 0 = <> AArch32 Media and VFP Features 1 = <>
I would swap these so we print when SEVL is implemented, otherwise we print something when no 32-bit support is present.