gicv3_its: Leave LPI interrupts enable during handling

[scottph]

Summary

This follows the behavior on x86 where edge triggered interrupts
are not disabled when executing the handler. Because the ITS is a
shared resource, contention for the command queue lock can be
substantial.

Suggested by: gallatin
Sponsored by: Ampere Computing LLC

[gallatin]

Are legacy interrupts supported on this platform? Is this code also used for legacy interrupts?

I was about to start on a patch which included a bool to tell if the interrupt was for msi/msi-x and only skip the enable/disable for msi/msi-x.

[andrew]

This driver only manages MSI/MSI-X interrupts.

[val_packett.cool]

In D28709#642658, @gallatin wrote:

Are legacy interrupts supported on this platform?

PCIe legacy interrupts do technically work on arm64, but at least in my experience, only with awful performance.
I've hit that twice: on Scaleway's ThunderX VPS service (R.I.P.) for some reason MSI was blacklisted so virtio was awfully slow because of legacy, and (tested on the MACCHIATObin but applicable probably everywhere) AMD Radeon GPUs were wasting CPU on hundreds of thousands of interrupts per second when legacy was used (fixed by enabling MSI in drm with D21008 / https://github.com/FreeBSDDesktop/kms-drm/pull/163).

[jhb]

I think this is fine. If you ever have real level-triggered interrupts in the future you'll have to fix this to mask them for those.

[gallatin]

I've tested this on a Netflix server, and can confirm that it works fine, and eliminates spinlock contention on the gic cmd queue.