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riscv pmap: zero reserved pte bits in ppn
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Authored by freebsdphab-AX9_cmx.ietfng.org on Jun 30 2020, 8:08 PM.

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Summary

The top 10 bits of a pte are reserved by specification and are not part of the PPN

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rS FreeBSD src repository
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kp added a subscriber: kp.

For those playing along at home, from 'Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified', '4.4.1 Addressing and Memory Protection', page 72: "The PTE format for Sv39 is shown in Figure 4.18. Bits 9–0 have the same meaning as for Sv32. Bits 63–54 are reserved for future use and must be zeroed by software for forward compatibility.".

This revision is now accepted and ready to land.Jul 1 2020, 1:30 PM
mhorne added inline comments.
sys/riscv/riscv/pmap.c
362 ↗(On Diff #73923)

I'd prefer to see a definition for the constant placed in pte.h, something like PTE_MASK.
Also, rather than splitting the expression in the middle, you could do:

#define PTE_TO_PHYS(pte) \
    ((((pte) & PTE_MASK) >> PTE_PPN0_S) * PAGE_SIZE)

(The second line has a 4-space indent)

This revision now requires review to proceed.Jul 1 2020, 5:20 PM
This revision is now accepted and ready to land.Jul 1 2020, 5:33 PM

@mhorne Do you want to commit or shall I?

In D25523#564539, @kp wrote:

@mhorne Do you want to commit or shall I?

Would you? Alongside D25524 if you don't mind.

This revision was automatically updated to reflect the committed changes.