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riscv pmap: zero reserved pte bits in ppn

Description

riscv pmap: zero reserved pte bits in ppn

The top 10 bits of a pte are reserved by specification[1] and are not part of
the PPN.

[1] 'Volume II: RISC-V Privileged Architectures V20190608-Priv-MSU-Ratified',
'4.4.1 Addressing and Memory Protection', page 72: "The PTE format for Sv39 is
shown in Figure 4.18. ... Bits 63–54 are reserved for future use and must be
zeroed by software for forward compatibility."

Submitted by: Nathaniel Filardo <nwf20@cl.cam.ac.uk>
Reviewed by: kp, mhorne
Differential Revision: https://reviews.freebsd.org/D25523

Details

Provenance
kpAuthored on
Reviewer
kp
Differential Revision
D25523: riscv pmap: zero reserved pte bits in ppn
Parents
rS362852: riscv locore.S: load constant prior to loop
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