The barrier is required on ARM and ARM64 to prevent reording of data
fetch, which could cause race between drbr_enqueue and drbr_peek.
If the buffer will be fetched in drbr_peek before checking if there are
buffers in the drbr ring, the invalid memory address could be stored, but the
condition could be true if the buffer will be added in the meantime in
the drbr_enqueue.
This will cause in returning invalid buffer address by drbr_peek.