intelhfi - Intel TD/HFI driver - Part1b: Add IA32_PM_ENABLE bit flag define for specialregs.h.
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Authored by koinec_yahoo.co.jp on Sun, May 10, 11:40 AM.

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minsoochoo0122_proton.me
kib
olce

Commits

rG436f47a80c20: intelhfi: Add IA32_PM_ENABLE bit flag define

Summary

To support hmp(4) (https://reviews.freebsd.org/D56547) in the intelhfi driver being developed at https://reviews.freebsd.org/D44456, it became necessary to process the IA32_PM_ENABLE MSR.
Therefore, I will add the definition of the corresponding bit flag.

The following is supplementary information:

This flag is a separate patch from intelhfi (https://reviews.freebsd.org/D44456). This is because it allows for future support of the hwpstate_intel driver, which currently hardcodes the numerical value.
Applying this patch is also necessary to build intelhfi (https://reviews.freebsd.org/D44456).

Test Plan

This code utilizes constants defined in intelhfi (https://reviews.freebsd.org/D44456), and I've confirmed that the values can be obtained by this test.

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koinec_yahoo.co.jp requested review of this revision.Sun, May 10, 11:40 AM

koinec_yahoo.co.jp created this revision.

koinec_yahoo.co.jp mentioned this in D44456: intelhfi - Intel TD/HFI driver - Part4: Add intelhfi driver's source-code & Makefile..Sun, May 10, 12:07 PM

minsoochoo0122_proton.me requested changes to this revision.Sun, May 10, 2:29 PM

minsoochoo0122_proton.me added reviewers: kib, olce.

minsoochoo0122_proton.me set the repository for this revision to rG FreeBSD src repository.

minsoochoo0122_proton.me added subscribers: emaste, imp, kib, olce.

minsoochoo0122_proton.me added inline comments.

sys/x86/include/specialreg.h
908	Like above, you can simply use `0x00000001`,

This revision now requires changes to proceed.Sun, May 10, 2:29 PM

emaste added inline comments.Mon, May 11, 2:49 PM

sys/x86/include/specialreg.h
908	Values below are of the form `(1ULL << x)` though and I think it's fine. From the Intel doc: HWP_ENABLE (bit 0, R/W1Once) — Software sets this bit to enable HWP with autonomous selection. When set, the processor will disregard input from the legacy performance control interface (IA32_PERF_CTL). Note this bit can only be enabled once from the default value. Once set, writes to the HWP_ENABLE bit are ignored. Only RESET will clear this bit. Default = zero (0). So if the source doc uses "bit 0" I think `(1ULL << 0)` is straightforward.

Makes sense, LGTM.

This revision is now accepted and ready to land.Mon, May 11, 3:55 PM

I'm happy to push this bit definition now and get one item out of the stack. Can you confirm Koine Yuusuke <koinec@yahoo.co.jp> for the Git author info?