This is the first major errata we need to support in order to run on
current T-HEAD/XuanTie CPUs, e.g. the C906 or C910, found in several
existing RISC-V SBCs. With these custom dcache routines installed,
busdma can reliably communicate with devices which are not coherent
w.r.t. the CPU's data caches.

This patch introduces the first errata handling functions to identcpu.c,
and thus is forced to make some decisions about how this code is
structured. It will be amended with the changes that follow in the
series, yet I feel the final result is (unavoidably) somewhat clumsy. I
expect the CPU identification code will continue to evolve as more CPUs
and their errata are eventually supported.

T-HEAD specific code is added to a new file, and the custom instructions
can fortunately be enabled on a per-function basis.