x86: Allow sharing of perfomance counter interrupts
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Authored by bnovkov on Aug 23 2024, 4:34 PM.

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br
kib
markj
gnn

Summary

This patch refactors the Performance Counter interrupt setup code to allow sharing the interrupt line between multiple drivers.
More specifically, Performance Counter interrupts are used by both hwpmc(4) and hwt(4)'s Intel Processor Trace backend.

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rG FreeBSD src repository

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bnovkov created this revision.Aug 23 2024, 4:34 PM

Herald added a reviewer: gnn. · View Herald TranscriptAug 23 2024, 4:34 PM

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bnovkov requested review of this revision.Aug 23 2024, 4:34 PM

bnovkov added a child revision: D46421: x86: Refactor kernel-mode NMI handling .

kib added inline comments.Aug 23 2024, 6:56 PM

sys/x86/x86/local_apic.c
816–817	Why do we need these braces? Why not provide pcint() services regardless of hwpmc/hwt? IMO it is more logical, and slight unconditional code addition does not matter for amd64. But we reduce the ifdef maze then.