riscv intc: convert to a bus

[br]

Summary

Convert RISC-V intc device to a bus, and establish parent-child relationships with IMSIC

That would allow to propagate PIC_INIT_SECONDARY() call to the child

This is similar to what gicv5 does with IRS department

Test Plan

Tested on Spacemit K3 with IMSIC.

[jrtc27]

Please go read all of D40474

[br]

In D59813#1372460, @jrtc27 wrote:

Please go read all of D40474

I think this comment by @mmel is most useful

I've written this several times in other reviews, I think. Initialization of PICs on secondary cores must be coordinated with the parent PIC and must follow the PIC hierarchy. Imho, the only way to do this correctly is implement this in pic_init_secondary() for each PIC driver.

BTW - most real systems have multiple PIC instances - GICv3 has multiple functions/departments, each of which is a separate PIC, each PCI driver should contain a PIC. And it's not uncommon for a hierarchy to have 3 or 4 nodes.

[br]

Another idea draft for discussion

[mmel]

You're definitely right, from an INTRNG point of view. Thanks.

sys/riscv/riscv/intc.c

335

You should initialize the child PIC before enabling the interrupts on this PIC.
A safer way would be to disable the interrupts on this PIC, initialize the child PICs, and then re-enable them.

[br]

Initialize the child PIC with interrupts disabled on the root PIC

[jrtc27]

I intend to review this in the coming days

[mhorne]

I think this is quite clean.

We'll let @jrtc27 weigh in.