AMD64 Architecture Programmer's Manual Volume 3 says the following:
ECX[15:0] contains a count of the number of sequential pages to
invalidate in addition to the original virtual address, starting from
the virtual address specified in rAX. A count of 0 invalidates a
single page. ECX[31]=0 indicates to increment the virtual address at
the 4K boundary. ECX[31]=1 indicates to increment the virtual address
at the 2M boundary. The maximum count supported is reported in
CPUID function 8000_0008h, EDX[15:0].
ECX[31] being what we call INVLPGB_2M_CNT, signaling to increment the
VA by 2M.
This instruction invalidates the TLB entry or entries, regardless of
the page size (4 Kbytes, 2 Mbytes, 4 Mbytes, or 1 Gbyte). [...]
Combined with this, my interpretation of the current code is: if
<va> is aligned on a PDE boundary, we'll use INVLPGB_2M_CNT to try and
invalidate <cnt> PDEs with a single call, but that only works if <va> is
the start of at least <cnt> 2M pages. Otherwise, if <va> or any of the
subsequent PDEs isn't actually a superpage, then we would actually only
invalidate the *first* page within the PDE before skipping to the next
PDE, leaving the remainder of the 4K pages in between as they were.
The implication would seem to be that we would need to inspect the range
that we're trying to invalidate if we're planning on using
INVLPGB_2M_CNT at all, so this patch just simplifies it to a series of
4K invalidations. My gut feeling is that we likely still come out on
top vs. the TLB shootdown we're avoiding.
This seems to explain some issues we've seen lately with fdgrowtable()
and kqueue on recent Zen4/Zen5 EPYC hardware, where we'd experience
corruption that we can't explain.
PR: 293382