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sdhci_fsl_fdt: Provide more accurate clk calculation

Authored by on Oct 28 2021, 1:37 PM.



SDHCI controllers found in the QorIQ SoCs offer improved accuracy of
the clock frequency selection, compared to the SDHCI standard. Frequency
selection is performed using two divider registers, named prescaler and
divisor, according to the following formula:
frequency = base clock / (prescaler * divisor), where prescaler can be
bypassed (set to 1) and divisor permitted to take odd values.

Rather than depend on clock division precalculated by sdhci core, make
use of this property of the divider registers and achieve frequencies
closer to the ones requested.

Submitted by: Artur Rojek <>
Obtained from: Semihalf
Sponsored by: Alstom Group

Diff Detail

R10 FreeBSD src repository
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Automatic diff as part of commit; unit tests not applicable.

Event Timeline

This revision was not accepted when it landed; it landed in state Needs Review.Nov 5 2021, 9:21 AM
This revision was automatically updated to reflect the committed changes.