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pci: Add Synopsys Designware PCIe controller quirk
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Authored by pan_semihalf.com on Thu, Sep 9, 7:26 AM.

Details

Summary

The Synopsys Designware PCIe controller causes devices on bus 0 to
appear twice. This is mitigated by manually blocking slots 1 and
higher on bus 0.

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Repository
R10 FreeBSD src repository
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Event Timeline

pan_semihalf.com created this revision.
greg_unrelenting.technology added inline comments.
sys/dev/pci/pci_host_generic.h
91

maybe name it PCIE_ECAM_DESIGNWARE_QUIRK? Armada8k is not the only SoC with this quirk…

sys/dev/pci/pci_host_generic_acpi.c
103

I guess we won't need any more entries here unlike the FDT case because

sys/dev/pci/pci_host_generic_fdt.c
153

Linux also applies it for socionext,synquacer-pcie-ecam and the SoC-vendor-neutral snps,dw-pcie-ecam

  • Rename quirk to PCIE_ECAM_DESIGNWARE_QUIRK
  • Add socionext,synquacer-pcie-ecam and snps,dw-pcie-ecam compats

LGTM + tested with ACPI and DT on MacchiatoBin.

sys/dev/pci/pci_host_generic_acpi.c
103

Fortunately Marvell version of this IP does not have the necessity of the root port hiding, so it's much simpler. WRT the Amazon version,

This revision is now accepted and ready to land.Wed, Sep 15, 10:18 AM