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plic: improve enable bit handling
Needs ReviewPublic

Authored by mhorne on Mon, Oct 7, 11:01 PM.

Details

Reviewers
markj
br
kp
Summary

The RISC-V PLIC provides per-context enable bits for each interrupt.
Currently, we only set the enable bit of the current context, when
really we want to enable/disable interrupts for all relevant contexts.

Also, interrupts are only initialized properly for the boot processor.
APs were relying on the fact that BBL enables all PLIC interrupts by
default, but this is not the case with OpenSBI. Fix this by initializing
all enable and threshold bits to a consistent state across all CPUs.

Test Plan

The system can boot successfully to multi-user mode with both BBL and
OpenSBI and any number of CPUs.

Diff Detail

Lint
Lint OK
Unit
No Unit Test Coverage
Build Status
Buildable 26919
Build 25224: arc lint + arc unit

Event Timeline

mhorne created this revision.Mon, Oct 7, 11:01 PM