The RISC-V PLIC provides per-context enable bits for each interrupt.
Currently, we only set the enable bit of the current context, when
really we want to enable/disable interrupts for all relevant contexts.
Also, interrupts are only initialized properly for the boot processor.
APs were relying on the fact that BBL enables all PLIC interrupts by
default, but this is not the case with OpenSBI. Fix this by initializing
all enable and threshold bits to a consistent state across all CPUs.