Change Details

The RISC-V PLIC provides per-context enable bits for each interrupt. Currently, we only set the enable bit of the current context, when really we want to enable/disable interrupts for all relevant contexts. Also, interrupts are only initialized properly for the boot processor. APs were relying on the fact that BBL enables all PLIC interrupts by default, but this is not the case with OpenSBI. Fix this by initializing all enable and threshold bits to a consistent state across all CPUs.

Our PLIC implementation only enables interrupts on the boot hart. Implement plic_bind_intr() so that they can be redistributed near the end of boot during intr_irq_shuffle(). This also slightly modifies how enable bits are handled in an attempt to better fit the PIC interface. plic_enable_intr/plic_disable_intr are converted to manage an interrupt source's threshold value, since this value can be used as to globally enable/disable an irq. All handing of the per-context enable bits is moved to the new methods plic_setup_intr() and plic_bind_intr().

The RISC-VOur PLIC provides per-contextimplementation only enable bits for each interrupts interrupts on the boot hart. Currently, we only set the enable bit of the current context, whenImplement plic_bind_intr() so that they can be redistributed near the really we want to enable/disableend of boot during interrupts for all relevant contextsr_irq_shuffle(). Also, interrupts are only initialized properly for the boot processor.This also slightly modifies how enable bits are handled in an attempt to APs were relying on the fact that BBL better fit the PIC interface. plic_enables all PLIC interrupts by_intr/plic_disable_intr are defaultconverted to manage an interrupt source's threshold value, butsince this is not the case with OpenSBI value can be used as to globally enable/disable an irq. Fix this by initializingAll handing of the allper-context enable and threshold bits to a consistent state across all CPUsbits is moved to the new methods plic_setup_intr() and plic_bind_intr().