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Enable arm,io-coherent property of PL310 L2 cache on Armada 38x platforms
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Authored by mw_semihalf.com on Jun 14 2017, 10:52 PM.
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Details

Summary

This patch disables outer cache sync in PL310 driver
by adding "arm,io-coherent" property. In addition to
the previous patches it was the last bit needed
for enabling proper operation of Armada 38x SoCs
with the IO cache coherency.

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rS FreeBSD src repository - subversion
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mw_semihalf.com edited the summary of this revision. (Show Details)

Add "arm,io-coherent" to PL310 node (see https://reviews.freebsd.org/D11245)

mw_semihalf.com retitled this revision from Enable dma-coherent bus property on Armada 38X to Enable arm,io-coherent property of PL310 L2 cache on Armada 38x platforms.
mw_semihalf.com edited the summary of this revision. (Show Details)

Do not add redundant 'dma-coherent', and add the property only for the PL310 node. Unlike linux, we do not have to do it in runtime, hacking the platform code.

This revision is now accepted and ready to land.Jun 21 2017, 1:57 PM
This revision was automatically updated to reflect the committed changes.