Page MenuHomeFreeBSD

Disable PL310 outer cache sync for IO coherent platforms

Authored by on Jun 17 2017, 10:05 AM.



When a PL310 cache is used on a system that provides hardware
coherency, the outer cache sync operation is useless, and can be
skipped. Moreover, on some systems, it is harmful as it causes
deadlocks between the Marvell coherency mechanism, the Marvell PCIe
or Crypto controllers and the Cortex-A9.

To avoid this, this commit introduces a new Device Tree property
'arm,io-coherent' for the L2 cache controller node, valid only for the
PL310 cache. It identifies the usage of the PL310 cache in an I/O
coherent configuration. Internally, it makes the driver disable the
outer cache sync operation.

Note, that other outer-cache operations are not removed, as they may
be needed for certain situations, such as booting secondary CPUs.
Moreover, in order to enable IO coherent operation, the decision
whether to use L2 cache maintenance callbacks is done in busdma
layer, which was enabled in one of the previous commits.

Diff Detail

rS FreeBSD src repository - subversion
Automatic diff as part of commit; lint not applicable.
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

I'm fine with rest.

490 ↗(On Diff #29745)

That's slightly creative way to get node for actual device :)
What about:

node = ofw_bus_get_node(dev);
if (OF_hasprop(node, "arm,io-coherent"))
           sc->sc_io_coherent = true;

Improve checking the "arm,io-coherent" property as pointed by @meloun-miracle-cz

This revision is now accepted and ready to land.Jun 18 2017, 3:44 AM
This revision was automatically updated to reflect the committed changes.