Fix HWPMC interrupt handling in Counting Mode
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Authored by mw_semihalf.com on May 25 2017, 3:31 PM.

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zbb
loos
arnaud.ysmal_stormshield.eu
fabient
bz

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rS319911: Fix HWPMC interrupt handling in Counting Mode

Summary

Fix support for Cycle Counter (evsel == 0xFF)
Stop and mask interrupts from all counters on init and finish

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rS FreeBSD src repository - subversion

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mw_semihalf.com created this revision.May 25 2017, 3:31 PM

Herald added subscribers: gnn, andrew, imp. · View Herald TranscriptMay 25 2017, 3:31 PM

mw_semihalf.com added a parent revision: D10909: Add detection of CPU class for ARMv6/v7.May 25 2017, 3:31 PM

mw_semihalf.com added a child revision: D10911: Fix event table for Cortex A9..

andrew added a reviewer: bz.May 26 2017, 1:16 PM

The 0xff should probably a #define somewhere but that's unrelated. I think we've done something similar for the timer code in the past; not sure in which review or tree that ended up.

Replace magic number with macro, as pointed by @bz

Thanks for the #define !

Closed by commit rS319911: Fix HWPMC interrupt handling in Counting Mode (authored by zbb). · Explain WhyJun 13 2017, 6:51 PM

This revision was automatically updated to reflect the committed changes.

Revision Contents
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Path

Size

sys/

dev/

hwpmc/

hwpmc_armv7.c

41 lines

sys/

pmc.h

1 line

Diff 29321

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sys/dev/hwpmc/hwpmc_armv7.c