Add PMC_CLASS_AMDIOMMU (0x1b) for the event counters of AMD IOMMU
units, with one row per counter of every unit the IOMMU driver
exports, and its 24 events in the order of their CSource values
0x01..0x18 (AMD 48882 rev 3.10): memory requests passed or translated,
IOMMU TLB and device table cache hits and misses, page table reads,
command processing, vAPIC and SMI events. Bump PMC_VERSION_MINOR and
make PMC_CLASS_LAST name the new class.

The counters count IOMMU activity, so only system-wide counting mode
is accepted and each counter has a single owner. As they see the DMA
of every device, allocation needs PRIV_PMC_SYSTEM even when
security.bsd.unprivileged_syspmcs is set. Qualifiers select the unit
and program the PASID, domain and requester ID match registers.
Counters in a bank whose match registers firmware has locked are not
used, as their matching cannot be controlled. Units whose rows would
not fit the 8-bit row index of a PMC id are left out.

A counter may be power-gated while no event is selected, as the Linux
driver allows for, so the event is selected before the counter is
loaded, and the count is saved before the event is deselected.

The class needs options IOMMU, acpi and pci, with the IOMMU driver
enabled (hw.amdiommu.enable=1); otherwise, as in an hwpmc.ko built
outside a kernel build, hwpmc_amdiommu.c only provides stubs that
report no counters. On AMD CPUs the class takes the slot between
PERF's and RAPL's and is initialized before RAPL, because
pmc_initialize() renumbers the classes' rows in slot order. The PERF
slot index is now only computed when the PERF MSRs are present.

libpmc allocates the events on amd64, with the optional unit=, devid=,
domain= and pasid= qualifiers; empty, signed, repeated and out of
range values are rejected. pmc.amdiommu.3 documents the class, its
events and qualifiers, and that events such as MEM_TRANS_TOTAL only
see the DMA of devices with an IOMMU context (hw.iommu.dma=1); pmc.3
lists the class.

Tested on an EPYC 9654, which does not power-gate the counters: the
requester ID and domain filters, and a non-matching PASID filter. A
matching PASID filter was not tested, for lack of PASID-tagged DMA.

Relnotes: yes
Sponsored by: AMD
Signed-off-by: Osvaldo Janeri Filho <ojanerif@amd.com>