Check the class capabilities and rows, allocation of every event,
exclusive counter ownership across CPUs, rejection of process-mode
requests by libpmc and by hwpmc(4), release of the counters of a killed
owner, qualifier parsing and unit selection. The tests skip unless the
machine has AMD IOMMU performance counters.
The DMA tests read a raw CAM disk and take the IOMMU unit and requester
ID of its controller from the controller's %iommu property. They skip
unless the disk DMA goes through a context of that unit; when it does,
the unit's counter must count the DMA, a requester ID filter must
count the controller's DMA and nothing for a requester ID that no
device uses, and a stopped counter must keep its count and count again
after a restart.
Some tests cover bugs found while the class was written: counters
shared by owners on different CPUs, process-mode PMCs that panicked at
context switch, and class rows out of step with the MI row numbering,
which panicked when a process holding running counters was killed.
Suggested by: Davi Chaves Azevedo <davi.chavesazevedo@amd.com>
Sponsored by: AMD
Signed-off-by: Osvaldo Janeri Filho <ojanerif@amd.com>