x86/iommu: export AMD IOMMU performance counters to hwpmc(4)

[ojanerif_amd.com]

Summary

An AMD IOMMU that implements EFR[PCSup] has banks of 48-bit event
counters in its MMIO space. At attach, read their geometry from the
Counter Configuration register, where NCounter value 1 is reserved,
and publish the unit under its device unit number. amd_pc.h declares
the lookup, the counter register accessors and a check of the bank
lock registers for the amd64 hwpmc(4) class added later.

A published unit is never withdrawn, because detach is not supported;
note that in amdiommu_detach().

Sponsored by: AMD
Signed-off-by: Osvaldo Janeri Filho <[e-mail]>

[kib]

sys/x86/iommu/amd_drv.c

513

Attach happens during device enumeration, under the Giant, single-threaded. You might safely use plain assignments there, and do not need acquire loads for derefs. Unless IOMMU can be hot-plugged (I am not sure), and FreeBSD gains hot-plug support for iommus, it is not needed.

OTOH, rel/acq are really plain stores/loads, so it is not too important.

[ojanerif_amd.com]

Thank you. Done.