arm64: Add MRS_SAFE to hold a safe ID field value
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Authored by andrew on Oct 15 2024, 2:01 PM.

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Reviewers

manu
imp

Group Reviewers

arm64

Commits

rGffdf9db281f5: arm64: Add MRS_SAFE to hold a safe ID field value

Summary

To support reworking the arm64 CPU ID code to add CTR_EL0, the cache
type register, start to move the safe value to be encoded as a named
field rather than part of MRS_EXACT.

Diff Detail

Repository

rG FreeBSD src repository

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Unit

Tests Skipped

Build Status

Buildable 60000
Build 56885: arc lint + arc unit

Event Timeline

andrew created this revision.Oct 15 2024, 2:01 PM

Herald added a reviewer: manu. · View Herald TranscriptOct 15 2024, 2:01 PM

Herald added subscribers: emaste, imp. · View Herald Transcript

andrew requested review of this revision.Oct 15 2024, 2:01 PM

Harbormaster completed remote builds in B60000: Diff 144905.Oct 15 2024, 2:01 PM

andrew added a parent revision: D47119: arm64: Support non-4 bit ID reg fields.Oct 15 2024, 2:01 PM

andrew added a child revision: D47121: arm64: Use a bit to hold userspace ID reg exports.

imp accepted this revision.Oct 15 2024, 2:21 PM

This revision is now accepted and ready to land.Oct 15 2024, 2:21 PM

Closed by commit rGffdf9db281f5: arm64: Add MRS_SAFE to hold a safe ID field value (authored by andrew). · Explain WhyOct 21 2024, 12:24 PM

This revision was automatically updated to reflect the committed changes.

andrew added a commit: rGffdf9db281f5: arm64: Add MRS_SAFE to hold a safe ID field value.

Revision Contents
Changeset List

Path

Size

sys/

arm64/

identcpu.c

10 lines

Diff 144905

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sys/arm64/arm64/identcpu.c

arm64: Add MRS_SAFE to hold a safe ID field valueClosedPublicActions