arm64: Support non-4 bit ID reg fields
ClosedPublic
Actions

Authored by andrew on Oct 15 2024, 2:01 PM.

Tags

None

Referenced Files

	Unknown Object (File)
	Mon, May 11, 8:18 PM

	Unknown Object (File)
	Mon, May 11, 8:18 PM

	Unknown Object (File)
	Mon, May 11, 8:05 PM

	Unknown Object (File)
	Sun, May 3, 12:29 AM

	Unknown Object (File)
	Thu, Apr 30, 7:42 AM

	Unknown Object (File)
	Mon, Apr 27, 7:54 PM

	Unknown Object (File)
	Apr 23 2026, 6:29 AM

	Unknown Object (File)
	Apr 21 2026, 12:16 PM

View All 90 Files

Subscribers

emaste

imp

Details

Reviewers

manu
imp

Group Reviewers

arm64

Commits

rGaa760039c6eb: arm64: Support non-4 bit ID reg fields

Summary

In preparation for using the ID register decode with the cache type
register support a non-4 bit field width.

Diff Detail

Repository

rG FreeBSD src repository

Lint

Lint Not Applicable

Unit

Tests Not Applicable

Event Timeline

andrew created this revision.Oct 15 2024, 2:01 PM

Herald added a reviewer: manu. · View Herald TranscriptOct 15 2024, 2:01 PM

Herald added subscribers: emaste, imp. · View Herald Transcript

andrew requested review of this revision.Oct 15 2024, 2:01 PM

Harbormaster completed remote builds in B59999: Diff 144904.Oct 15 2024, 2:01 PM

andrew added a parent revision: D47118: arm64: Add ID register field width values.Oct 15 2024, 2:01 PM

andrew added a child revision: D47120: arm64: Add MRS_SAFE to hold a safe ID field value.

imp accepted this revision.Oct 15 2024, 2:20 PM

This revision is now accepted and ready to land.Oct 15 2024, 2:20 PM

Closed by commit rGaa760039c6eb: arm64: Support non-4 bit ID reg fields (authored by andrew). · Explain WhyOct 21 2024, 12:24 PM

This revision was automatically updated to reflect the committed changes.

andrew added a commit: rGaa760039c6eb: arm64: Support non-4 bit ID reg fields.

Revision Contents
Changeset List

Path

Size

sys/

arm64/

identcpu.c

17 lines

Diff 145253

View Options

sys/arm64/arm64/identcpu.c

arm64: Support non-4 bit ID reg fieldsClosedPublicActions