Sort the names of the arm64 debug registers

[andrew]

Summary

While here clean up the names for the naming convention of the other
registers in this file.

Sponsored by: The FreeBSD Foundation

[mhorne]

sys/arm64/include/armreg.h

1106

Why were these ones given UL()?

[kib]

sys/arm64/include/armreg.h

136

These are called Debug Breakpoint Control Registers, at least in my copy of ARMARM

sys/arm64/arm64/debug_monitor.c

 #if defined(DDB) || defined(GDB)
 void
 kdb_cpu_set_singlestep(void)
 {
 
         KASSERT((READ_SPECIALREG(daif) & PSR_D) == PSR_D,
             ("%s: debug exceptions are not masked", __func__));
 
-        kdb_frame->tf_spsr |= DBG_SPSR_SS;
+        kdb_frame->tf_spsr |= PSR_SS;
         WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) |
-            DBG_MDSCR_SS | DBG_MDSCR_KDE);
+            MDSCR_SS | MDSCR_KDE);
 
         /*
          * Disable breakpoints and watchpoints, e.g. stepping
          * over watched instruction will trigger break exception instead of
          * single-step exception and locks CPU on that instruction for ever.
          */
         if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) {
                 WRITE_SPECIALREG(mdscr_el1,
-                    READ_SPECIALREG(mdscr_el1) & ~DBG_MDSCR_MDE);
+                    READ_SPECIALREG(mdscr_el1) & ~MDSCR_MDE);
         }
 }
 
 void
 kdb_cpu_clear_singlestep(void)
 {
 
         KASSERT((READ_SPECIALREG(daif) & PSR_D) == PSR_D,
             ("%s: debug exceptions are not masked", __func__));
 
         WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) &
-            ~(DBG_MDSCR_SS | DBG_MDSCR_KDE));
+            ~(MDSCR_SS | MDSCR_KDE));
 
         /* Restore breakpoints and watchpoints */
         if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) {
                 WRITE_SPECIALREG(mdscr_el1,
-                    READ_SPECIALREG(mdscr_el1) | DBG_MDSCR_MDE);
+                    READ_SPECIALREG(mdscr_el1) | MDSCR_MDE);
 
                 if ((kernel_monitor.dbg_flags & DBGMON_KERNEL) != 0) {
                         WRITE_SPECIALREG(mdscr_el1,
-                            READ_SPECIALREG(mdscr_el1) | DBG_MDSCR_KDE);
+                            READ_SPECIALREG(mdscr_el1) | MDSCR_KDE);
                 }
         }
 }
 
 int
 kdb_cpu_set_watchpoint(vm_offset_t addr, vm_size_t size, int access)
 {
         enum dbg_access_t dbg_access;
dbg_register_sync(struct debug_monitor_state *monitor)
         uint64_t mdscr;
         int i;
 
         if (monitor == NULL)
                 monitor = &kernel_monitor;
 
         mdscr = READ_SPECIALREG(mdscr_el1);
         if ((monitor->dbg_flags & DBGMON_ENABLED) == 0) {
-                mdscr &= ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE);
+                mdscr &= ~(MDSCR_MDE | MDSCR_KDE);
         } else {
                 for (i = 0; i < dbg_breakpoint_num; i++) {
                         dbg_wb_write_reg(DBG_REG_BASE_BCR, i,
                             monitor->dbg_bcr[i]);
                         dbg_wb_write_reg(DBG_REG_BASE_BVR, i,
                             monitor->dbg_bvr[i]);
                 }
 
                 for (i = 0; i < dbg_watchpoint_num; i++) {
                         dbg_wb_write_reg(DBG_REG_BASE_WCR, i,
                             monitor->dbg_wcr[i]);
                         dbg_wb_write_reg(DBG_REG_BASE_WVR, i,
                             monitor->dbg_wvr[i]);
                 }
-                mdscr |= DBG_MDSCR_MDE;
+                mdscr |= MDSCR_MDE;
                 if ((monitor->dbg_flags & DBGMON_KERNEL) == DBGMON_KERNEL)
-                        mdscr |= DBG_MDSCR_KDE;
+                        mdscr |= MDSCR_KDE;
         }
         WRITE_SPECIALREG(mdscr_el1, mdscr);
         isb();
 }
 
 void
 dbg_monitor_init(void)
 {
for (i = 0; i < dbg_watchpoint_num; i++) {
                         dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
                 }
 
                 for (i = 0; i < dbg_breakpoint_num; ++i) {
                         dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
                         dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
                 }
                 WRITE_SPECIALREG(mdscr_el1,
-                    READ_SPECIALREG(mdscr_el1) &
-                    ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE));
+                    READ_SPECIALREG(mdscr_el1) & ~(MDSCR_MDE | MDSCR_KDE));
                 isb();
         }
 }
 
 void
 dbg_monitor_exit(struct thread *thread, struct trapframe *frame)
 {
         int i;
for (i = 0; i < dbg_watchpoint_num; i++) {
                         dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
                 }
 
                 for (i = 0; i < dbg_breakpoint_num; ++i) {
                         dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
                         dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
                 }
                 WRITE_SPECIALREG(mdscr_el1,
-                    READ_SPECIALREG(mdscr_el1) &
-                    ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE));
+                    READ_SPECIALREG(mdscr_el1) & ~(MDSCR_MDE | MDSCR_KDE));
                 isb();
         }
 }

sys/arm64/arm64/exec_machdep.c

for (i = 0; i < DBG_BRP_MAX; i++) {
                 /*
                  * Some control fields are ignored, and other bits reserved.
                  * Only unlinked, address-matching breakpoints are supported.
                  *
                  * XXX: fields that appear unvalidated, such as BAS, have
                  * constrained undefined behaviour. If the user mis-programs
                  * these, there is no risk to the system.
                  */
-                ctrl &= DBG_BCR_EN | DBG_BCR_PMC | DBG_BCR_BAS;
-                if ((ctrl & DBG_BCR_EN) != 0) {
+                ctrl &= DBGBCR_EN | DBGBCR_PMC | DBGBCR_BAS;
+                if ((ctrl & DBGBCR_EN) != 0) {
                         /* Only target EL0. */
-                        if ((ctrl & DBG_BCR_PMC) != DBG_BCR_PMC_EL0)
+                        if ((ctrl & DBGBCR_PMC) != DBGBCR_PMC_EL0)
                                 return (EINVAL);
 
                         monitor->dbg_enable_count++;
                 }
 
                 monitor->dbg_bvr[i] = addr;
                 monitor->dbg_bcr[i] = ctrl;
         }
 
         for (i = 0; i < DBG_WRP_MAX; i++) {
                 addr = regs->db_watchregs[i].dbw_addr;
                 ctrl = regs->db_watchregs[i].dbw_ctrl;
 
                 /*
                  * Don't let the user set a watchpoint on a kernel or
                  * non-canonical user address.
                  */
                 if (addr >= VM_MAXUSER_ADDRESS)
                         return (EINVAL);
 
                 /*
                  * Some control fields are ignored, and other bits reserved.
                  * Only unlinked watchpoints are supported.
                  */
-                ctrl &= DBG_WCR_EN | DBG_WCR_PAC | DBG_WCR_LSC | DBG_WCR_BAS |
-                    DBG_WCR_MASK;
+                ctrl &= DBGWCR_EN | DBGWCR_PAC | DBGWCR_LSC | DBGWCR_BAS |
+                    DBGWCR_MASK;
 
-                if ((ctrl & DBG_WCR_EN) != 0) {
+                if ((ctrl & DBGWCR_EN) != 0) {
                         /* Only target EL0. */
-                        if ((ctrl & DBG_WCR_PAC) != DBG_WCR_PAC_EL0)
+                        if ((ctrl & DBGWCR_PAC) != DBGWCR_PAC_EL0)
                                 return (EINVAL);
 
                         /* Must set at least one of the load/store bits. */
-                        if ((ctrl & DBG_WCR_LSC) == 0)
+                        if ((ctrl & DBGWCR_LSC) == 0)
                                 return (EINVAL);
 
                         /*
                          * When specifying the address range with BAS, the MASK
                          * field must be zero.
                          */
-                        if ((ctrl & DBG_WCR_BAS) != DBG_WCR_BAS_MASK &&
-                            (ctrl & DBG_WCR_MASK) != 0)
+                        if ((ctrl & DBGWCR_BAS) != DBGWCR_BAS &&
+                            (ctrl & DBGWCR_MASK) != 0)
                                 return (EINVAL);
 
                         monitor->dbg_enable_count++;
                 }
                 monitor->dbg_wvr[i] = addr;
                 monitor->dbg_wcr[i] = ctrl;
         }
 

sys/arm64/arm64/swtch.S

 #include <machine/asm.h>
 #include <machine/armreg.h>
 
 __FBSDID("$FreeBSD$");
 
 .macro clear_step_flag pcbflags, tmp
         tbz     \pcbflags, #PCB_SINGLE_STEP_SHIFT, 999f
         mrs     \tmp, mdscr_el1
-        bic        \tmp, \tmp, #1
+        bic        \tmp, \tmp, #MDSCR_SS
         msr     mdscr_el1, \tmp
         isb
 999:
 .endm
 
 .macro set_step_flag pcbflags, tmp
         tbz     \pcbflags, #PCB_SINGLE_STEP_SHIFT, 999f
         mrs     \tmp, mdscr_el1
-        orr        \tmp, \tmp, #1
+        orr        \tmp, \tmp, #MDSCR_SS
         msr     mdscr_el1, \tmp
         isb
 999:
 .endm
 
 /*
  * void cpu_throw(struct thread *old, struct thread *new)
  */

sys/arm64/arm64/trap.c

if (!undef_insn(0, frame))
                         call_trapsignal(td, SIGILL, ILL_PRVOPC,
                             (void *)frame->tf_elr, exception);
                 userret(td, frame);
                 break;
         case EXCP_SOFTSTP_EL0:
                 td->td_frame->tf_spsr &= ~PSR_SS;
                 td->td_pcb->pcb_flags &= ~PCB_SINGLE_STEP;
                 WRITE_SPECIALREG(mdscr_el1,
-                    READ_SPECIALREG(mdscr_el1) & ~DBG_MDSCR_SS);
+                    READ_SPECIALREG(mdscr_el1) & ~MDSCR_SS);
                 call_trapsignal(td, SIGTRAP, TRAP_TRACE,
                     (void *)frame->tf_elr, exception);
                 userret(td, frame);
                 break;
         default:
                 call_trapsignal(td, SIGBUS, BUS_OBJERR, (void *)frame->tf_elr,
                     exception);
                 userret(td, frame);