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Add arm64 CnP support
AcceptedPublic

Authored by andrew on Jan 4 2022, 12:38 PM.

Details

Reviewers
alc
markj
kib
manu
Group Reviewers
arm64
Summary

Set the Common not Private bit in the ttbr registers when supported on
arm64. This tells the hardware it can share the translation table
entries on multiple CPUs.

Diff Detail

Repository
rS FreeBSD src repository - subversion
Lint
Lint OK
Unit
No Unit Test Coverage
Build Status
Buildable 43953
Build 40841: arc lint + arc unit

Event Timeline

sys/arm64/arm64/pmap.c
6589

You could replace this boolean with the value to or ttbr with. Then you can avoid one jump in pmap_to_ttbr0().

6618

Unable is the strange term. Do you mean that userspace is not yet activated, so there is no address switching done?

BTW I do not see why do you need to do this from the callback, instead of setting the value before calling IPI.

Switch to using a flag we or in to the ttbr

This revision is now accepted and ready to land.Jan 10 2022, 12:24 PM

Reword the comment in pmap_set_cnp

This revision now requires review to proceed.Jan 17 2022, 4:37 PM
This revision is now accepted and ready to land.Jan 18 2022, 12:00 AM

I'm quite surprised to see this feature supported by the Graviton 2. I would only have expected to see this feature on micro-architectures that implement SMT/hyperthreading. In fact, the last paragraph of https://developer.arm.com/documentation/101811/0101/Address-spaces-in-AArch64 essentially says so. I wonder if it's simply a NOP on Graviton 2.

sys/arm64/arm64/pmap.c
6641–6642

I would suggest adding a comment explaining why you defer enabling CnP until all of the cores are running.