Set the Common not Private bit in the ttbr registers when supported on
arm64. This tells the hardware it can share the translation table
entries on multiple CPUs.
You could replace this boolean with the value to or ttbr with. Then you can avoid one jump in pmap_to_ttbr0().
Unable is the strange term. Do you mean that userspace is not yet activated, so there is no address switching done?
BTW I do not see why do you need to do this from the callback, instead of setting the value before calling IPI.
I'm quite surprised to see this feature supported by the Graviton 2. I would only have expected to see this feature on micro-architectures that implement SMT/hyperthreading. In fact, the last paragraph of https://developer.arm.com/documentation/101811/0101/Address-spaces-in-AArch64 essentially says so. I wonder if it's simply a NOP on Graviton 2.
I would suggest adding a comment explaining why you defer enabling CnP until all of the cores are running.