hwpmc: initialize arm64 counter/interrupt state

[mhorne]

Summary

Performance counters and overflow interrupts are assumed to be disabled
by default, but this is not guaranteed. Ensure we disable both during
per-cpu initialization, before enabling the PMU. Otherwise, some systems
(such as the Ampere eMAG) would experience an interrupt storm upon
loading the hwpmc module.

[emaste]

sys/dev/hwpmc/hwpmc_arm64.c

490

Is this really don't use arm64_pmcr_write because it issues isb or something like that? (I was confused when I first saw this, thinking "but we don't call arm64_pmcr_write")

[andrew]

sys/dev/hwpmc/hwpmc_arm64.c

490

The isb will be to make the register write visible, so in this case we should mention in the comment that we rely on the arm64_pmcr_write call below to issue the isb.

[mhorne]

sys/dev/hwpmc/hwpmc_arm64.c

490

No, it is "don't issue an isb here, as the call to arm64_pmc_write() below will do it regardless". I will clarify this in the comment.

[emaste]

sys/dev/hwpmc/hwpmc_arm64.c

490

Oh I see, I was looking only at the newly added lines.

[mhorne]

Improve the comment about when we issue an isb instruction.

[br]

good job