Allow the creation of 3 level page tables

[andrew]

Summary

The stage 2 arm64 page tables may need to start at a lower level. This
is because we may only be able to map a limited IPA range and trying
to use a full 4 levels will cause the CPU to fault in an unrecoverable
way.

To simplify the code we still allocate the full 4 levels, however level 0
will only ever be used to find the level 1 table used as the base. Handle
this by creating a dummy entry in the level 0 table to point to the level 1
table.

[markj]

sys/arm64/arm64/pmap.c

1693 ↗

(On Diff #75821)

Maybe s/we are releasing it/until pmap_release() is called/.

1961 ↗

(On Diff #75821)

Please avoid adding new uses of boolean_t, bool is fine.

1974 ↗

(On Diff #75821)

Aren't we leaking the L3 page?

6142 ↗

(On Diff #75821)

It might be nicer to precompute this value and store it in the pmap, otherwise we are re-computing an effectively constant value on every context switch. That is, store the root paddr in a common field so that we don't need to check pm_levels.

[andrew]

• Store the ttbr address so we don't need to walk the page tables
• Free pages in pmap_release
• Update the wording of a comment in pmap_pinit_stage

sys/arm64/arm64/pmap.c

1961 ↗

(On Diff #75821)

I used boolean_t as that's the return type of pmap_unwire_l3.

[andrew]

Load the free list in pmap_release