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arm64: update instruction set attribute register definitions
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Authored by mhorne on Aug 11 2020, 7:20 PM.

Details

Summary

This adds definitions for the latest additions to the AA64ISAR[01] ID
registers. This brings the definitions for these registers in sync with
ARMv8.6 initial spec release.

An upcoming change will parse many of these fields for HWCAP features.

Diff Detail

Repository
rS FreeBSD src repository
Lint
Automatic diff as part of commit; lint not applicable.
Unit
Automatic diff as part of commit; unit tests not applicable.

Event Timeline

markj added inline comments.
sys/arm64/arm64/identcpu.c
375 ↗(On Diff #75695)

"TLBIOS" and "TLBIOSR" perhaps?

This revision is now accepted and ready to land.Aug 11 2020, 9:13 PM
sys/arm64/arm64/identcpu.c
375 ↗(On Diff #75695)

We should give the macros better names, and report them differently so we can tell which we have from dmesg.

382–383 ↗(On Diff #75695)

Can you give the macros better names, e.g. _TS_CondM_8_4 and _TS_CondM_8_5

Improve the names of several macros.

This revision now requires review to proceed.Aug 12 2020, 3:10 PM
mhorne added inline comments.
sys/arm64/arm64/identcpu.c
540 ↗(On Diff #75730)

What is the distinction between MRS_EXACT and MRS_LOWER? I looked but had a hard time understanding the purpose.

sys/arm64/arm64/identcpu.c
540 ↗(On Diff #75730)

MRS_EXACT is shorthand for MRS_EXACT_VAL(0), i.e. always set the field to 0. MRS_LOWER will perform a comparison between the current and new field values and use the lower (signed or unsigned) of the two.

This revision is now accepted and ready to land.Aug 13 2020, 4:22 PM

Use MRS_LOWER for the new aa64isar1 fields. We want to expose them to userspace.

This revision now requires review to proceed.Aug 14 2020, 9:02 PM
This revision was not accepted when it landed; it landed in state Needs Review.Aug 15 2020, 2:58 PM
This revision was automatically updated to reflect the committed changes.