Enable SD/MMC (microSD and eMMC controllers) on the Rockchip RK3399 SoC

[val_packett.cool]

Summary

• Add SD/MMC related RK3399 clocks
• Add RK3399 to rockchip_dwmmc
• Add arasan,sdhci-5.1 to sdhci_fdt

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I've seen dwmmc not work before, but today I retested with a known good microSD card and it actually does work. (Slowly…)

Unfortunately, I don't have an eMMC module, so I can't fully test that, but at least I see that the controller attaches and the bus gets scanned.

rockchip_dwmmc0: <Synopsys DesignWare Mobile Storage Host Controller (RockChip)> mem 0xfe320000-0xfe323fff irq 11 on ofwbus0
rockchip_dwmmc0: Hardware version ID is 270a
mmc0: <MMC/SD bus> on rockchip_dwmmc0
sdhci_fdt0: <Arasan generic fdt SDHCI controller> mem 0xfe330000-0xfe33ffff irq 12 on ofwbus0
sdhci_fdt0-slot0: Hardware doesn't specify timeout clock frequency, setting BROKEN_TIMEOUT quirk.
sdhci_fdt0: 1 slot(s) allocated
mmc1: <MMC/SD bus> on sdhci_fdt0
…
mmcsd0: 16GB <SDHC USDU1 2.0 SN 42B594F0 MFG 01/2018 by 116 J`> at mmc0 50.0MHz/4bit/256-block
mmc1: No compatible cards found on bus

Test Plan

Anyone with an RK3399 board and an eMMC module?

[manu]

I have a patch locally that enable sd on rk3399, but I wanted to make the driver better before committing. I haven't check your clocks in this patch.
If you didn't test eMMC don't add it to your patch, I haven't looked at the arasan controller yet but I'm sure that if there is a different compatible it's because we need to do more work than just matching on the compatible.
Thanks

[manu]

You missed the gate for hclk_sdmmc (in CRU_CLKGATE_CON33) and maybe more.
The SD clocks matches what I have in my patch locally.
With r344527 commited sd is faster on RK3328, I'll test on RK3399 and commit my patch after.

[val_packett.cool]

In D19336#413879, @manu wrote:

I haven't looked at the arasan controller yet but I'm sure that if there is a different compatible it's because we need to do more work than just matching on the compatible.

Hm, sys/arm/broadcom/bcm2835/bcm2835_sdhci.c mentions "a bug where it may lose the content of consecutive writes to registers that are within two SD-card clock cycles of each other (a clock domain crossing problem)", but it might be specific to the revision of the arasan controller that's used on the broadcom SoC, and 5.1 might be fine.

[manu]

Just looking at https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt?id=4436a3711e3249840e0679e92d3c951bcaf25515#n64
The driver needs to handle phy (and we need a phy driver), the arasan,soc-ctl-syscon property (whatever it is used for) and deal with clocks.
So for me the mmc patch is a no go for now.
I've commited my sd patch in r344626 and r344627

[val_packett.cool]

new emmc patch is D20156