riscv: Include spibus and spigen in GENERIC
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Authored by jrtc27 on Jul 5 2021, 12:05 AM.

Details

Reviewers

mhorne
kp
philip

Group Reviewers

riscv

Commits

rG16ee8fe56b8b: riscv: Include spibus and spigen in GENERIC
rG8c439847f0d3: riscv: Include spibus and spigen in GENERIC

Summary

We already attempt to enable the SiFive SPI controller, but since spibus
isn't enabled it isn't actually built.

Diff Detail

Repository

rS FreeBSD src repository - subversion

Lint

Lint Passed

Unit

No Test Coverage

Build Status

Buildable 40274
Build 37163: arc lint + arc unit

Event Timeline

jrtc27 created this revision.Jul 5 2021, 12:05 AM

Herald added a subscriber: imp. · View Herald TranscriptJul 5 2021, 12:05 AM

jrtc27 requested review of this revision.Jul 5 2021, 12:05 AM

Harbormaster completed remote builds in B40274: Diff 91735.Jul 5 2021, 12:05 AM

kp accepted this revision as: kp.Jul 5 2021, 9:23 AM

This revision is now accepted and ready to land.Jul 5 2021, 9:23 AM

philip accepted this revision.Jul 5 2021, 3:44 PM

Closed by commit rG8c439847f0d3: riscv: Include spibus and spigen in GENERIC (authored by jrtc27). · Explain WhyJul 21 2021, 5:47 AM

This revision was automatically updated to reflect the committed changes.

jrtc27 added a commit: rG8c439847f0d3: riscv: Include spibus and spigen in GENERIC.

jrtc27 added a commit: rG16ee8fe56b8b: riscv: Include spibus and spigen in GENERIC.Sep 7 2021, 12:10 PM

Revision Contents
Changeset List

Path

Size

sys/

riscv/

conf/

GENERIC

3 lines

Diff 91735

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riscv: Include spibus and spigen in GENERICClosedPublicActions