bhyve/ioapic: improve the tracking of IRR bit
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Authored by royger on Jan 19 2021, 2:26 PM.

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rG38433b790de0: bhyve/ioapic: improve the tracking of IRR bit
rG5ea878684f6c: bhyve/ioapic: improve the tracking of IRR bit

Summary

One common method of EOI'ing an interrupt at the IO-APIC level is to
switch the pin to edge triggering mode and then back into level mode.
That would cause the IRR bit to be cleared and thus further interrupts
to be injected. FreeBSD does indeed use that method if the IO-APIC EOI
register is not supported.

The bhyve IO-APIC emulation code didn't clear the IRR bit when doing
that switch, and was also missing acknowledging the IRR state when
trying to inject an interrupt in vioapic_send_intr.

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rG FreeBSD src repository

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Event Timeline

royger created this revision.Jan 19 2021, 2:26 PM

Herald added a reviewer: bhyve. · View Herald TranscriptJan 19 2021, 2:26 PM

Herald added subscribers: bcran, rgrimes, imp. · View Herald Transcript

royger requested review of this revision.Jan 19 2021, 2:26 PM

Harbormaster completed remote builds in B36340: Diff 82570.Jan 19 2021, 2:26 PM

I tested all 3 ioapic diffs with a FreeBSD 12.2 guest on -current, with MSI/MSI-x disabled to force virtio-net and ahci to use level-triggered legacy IRQs. Some stress testing was done with those devices without any issue.

This revision is now accepted and ready to land.Feb 2 2021, 8:23 AM

Closed by commit rG5ea878684f6c: bhyve/ioapic: improve the tracking of IRR bit (authored by royger). · Explain WhyFeb 2 2021, 8:51 AM

This revision was automatically updated to reflect the committed changes.

royger added a commit: rG5ea878684f6c: bhyve/ioapic: improve the tracking of IRR bit.

jhb added a commit: rG38433b790de0: bhyve/ioapic: improve the tracking of IRR bit.Jan 26 2023, 6:35 PM