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Differential D59489

arm64/smmu: Only MSI poll when cache-coherent
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Authored by andrew on Mon, Sep 7, 4:13 PM.
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F171066525: D59489.id186140.diff
Tue, Sep 8, 12:25 PM
F171062203: D59489.diff
Tue, Sep 8, 11:41 AM
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F171024481: D59489.id186140.diff
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F170946518: D59489.id186140.diff
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Details

Reviewers
manu
Group Reviewers
arm64
Summary

Only use the MSI polling method when we support MSIs and the SMMU is
cache-coherent.

The SMMU writes to a memory location. If it is not cache-coherent then
the CPU may read the existing value in its cache and miss the signal
the sync operation has completed.

Sponsored by: Arm Ltd

Diff Detail

Repository
rG FreeBSD src repository
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Unit
Tests Skipped
Build Status
Buildable 76636
Build 73519: arc lint + arc unit

Revision Contents
Changeset List

PathSize
sys/
arm64/
iommu/
12 lines
2 lines
4 lines

Diff 186140

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sys/arm64/iommu/smmu.c

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sys/arm64/iommu/smmu_fdt.c

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sys/arm64/iommu/smmuvar.h

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