Page MenuHomeFreeBSD
Differential D59489

arm64/smmu: Only MSI poll when cache-coherent
ClosedPublic
Actions

Authored by andrew on Mon, Sep 7, 4:13 PM.
Tags
None
Referenced Files
F173793425: D59489.id186140.diff
Mon, Sep 28, 11:35 AM
Unknown Object (File)
Mon, Sep 28, 8:46 AM
Unknown Object (File)
Mon, Sep 28, 4:32 AM
Unknown Object (File)
Mon, Sep 28, 1:15 AM
Unknown Object (File)
Mon, Sep 28, 12:24 AM
Unknown Object (File)
Sun, Sep 27, 2:07 AM
Unknown Object (File)
Sun, Sep 27, 2:07 AM
Unknown Object (File)
Sun, Sep 27, 1:56 AM
View All 35 Files
Subscribers
emaste
imp

Details

Reviewers
manu
Group Reviewers
arm64
Commits
rG50e01b6351b1: arm64/smmu: Only MSI poll when cache-coherent
Summary

Only use the MSI polling method when we support MSIs and the SMMU is
cache-coherent.

The SMMU writes to a memory location. If it is not cache-coherent then
the CPU may read the existing value in its cache and miss the signal
the sync operation has completed.

Sponsored by: Arm Ltd

Diff Detail

Repository
rG FreeBSD src repository
Lint
Lint Not Applicable
Unit
Tests Not Applicable

Revision Contents
Changeset List

PathSize
sys/
arm64/
iommu/
12 lines
2 lines
4 lines

Diff 187338

View Options

sys/arm64/iommu/smmu.c

Loading...
View Options

sys/arm64/iommu/smmu_fdt.c

Loading...
View Options

sys/arm64/iommu/smmuvar.h

Loading...