This may have been called after intr_irq_shuffle. For most interrupt
controllers this appears to be safe, however for the GICv5 we need to
read a per-CPU ID register before we can assign interrupts to a given
CPU.

Fix the race by moving intr_pic_init_secondary earlier in the boot,
after devices have been enumerated and before the interrupts are moved
to their assigned CPUs.

Sponsored by: Arm Ltd