o Beef up hwpmc_mips(4) to support more than 2 performance counters on contemporary MIPSes (i.e. 74K and up);
o automatically probe and detect the number of supported counters;
o cleanup and diambiguate access to the PerfCntN and PerfCtlN registers.
Differential D5644
Add support for more than 2 perf counters into hwpmc_mips(4) Authored by sobomax on Mar 15 2016, 4:09 AM. Tags None Referenced Files
Details
o Beef up hwpmc_mips(4) to support more than 2 performance counters on contemporary MIPSes (i.e. 74K and up); o automatically probe and detect the number of supported counters; o cleanup and diambiguate access to the PerfCntN and PerfCtlN registers.
Diff Detail
Event Timeline |