LinuxKPI: Add pcie_capability_clear_and_set_word() function
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Authored by wulf on Nov 28 2023, 9:36 PM.

Details

Reviewers

manu
dumbbell
bz
jhb

Commits

rGa87884e34ec1: LinuxKPI: Add pcie_capability_clear_and_set_word() function
rG808ae4e29b6b: LinuxKPI: Add pcie_capability_clear_and_set_word() function

Summary

It does a Read-Modify-Write operation using clear and set bitmasks on
PCI Express Capability Register at pos. As certain PCI Express
Capability Registers are accessed concurrently in RMW fashion, hence
require locking which is handled transparently to the caller.

Sponsored by: Serenity CyberSecurity, LLC
MFC after: 1 week
MFC TODO: Move pcie_cap_lock to bottom to preserve KBI compatibility

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Repository

rG FreeBSD src repository

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No Test Coverage

Build Status

Buildable 54677
Build 51566: arc lint + arc unit

Event Timeline

wulf created this revision.Nov 28 2023, 9:36 PM

Herald added subscribers: linuxkpi, emaste, imp. · View Herald TranscriptNov 28 2023, 9:36 PM

wulf requested review of this revision.Nov 28 2023, 9:36 PM

Harbormaster completed remote builds in B54677: Diff 130707.Nov 28 2023, 9:36 PM

wulf added a reviewer: bz.Nov 28 2023, 10:49 PM

manu accepted this revision.Nov 29 2023, 6:19 AM

This revision is now accepted and ready to land.Nov 29 2023, 6:19 AM

How does that lock prevent us from any other changes at the same time by anything calling pcie_capability_write_word() in between?

This revision now requires changes to proceed.Dec 8 2023, 6:01 PM

Add locking in pcie_capability_set_word() and pcie_capability_clear_word()

In D42821#979762, @bz wrote:

How does that lock prevent us from any other changes at the same time by anything calling pcie_capability_write_word() in between?

It will not prevent. On Linux only pcie_capability_clear_and_set_word(), pcie_capability_clear_word() and pcie_capability_clear_and_set_word() are protected with this lock.

Even with the other locks it won't give us want we want. I assume it's likely okay to accept the race as otherwise we'd probably have to sort this out in the native PCI layer? @jhb?