The GPIO controls the multiplexing of the D1 pins to its peripherals,
so this adds the definitions needed by the aw_gpio driver to support
the D1.
Also, this modifies the aw_gpio driver to support the differences of
the D1 controller:
- pins can have up to 15 functions,
- each port is mapped with an alignment of 0x30,
- CFG registers have 4 bits per pin,
- DRV registers have 4 bits per pin,
- the offset of PULL registers is 0x24.
Signed-off-by: Julien Cassette <julien.cassette@gmail.com>