MCA: add AMD Error Thresholding support

[avg]

Summary

Currently the feature is implemented only for a subset of errors
reported via Bank 4. The subset includes only DRAM-related errors.

The new code builds upon and reuses the Intel CMC (Correctable MCE
Counters) support code. However, the AMD feature is quite different
and, unfortunately, much less regular.

For references please see AMD BKDGs for models 10h - 16h.
Specifically, see MSR0000_0413 NB Machine Check Misc (Thresholding)
Register (MC4_MISC0).
http://developer.amd.com/resources/developer-guides-manuals/

Test Plan

Tested with a processor from 10h family on a system where correctable
ECC errors occur semi-regularly, sometimes in bursts.

Here is an example of three consecutive MCE reports:

MCA: Bank 4, Status 0xdc544100e0080a13
MCA: Global Cap 0x0000000000000106, Status 0x0000000000000000
MCA: Vendor "AuthenticAMD", ID 0x100f43, APIC ID 0
MCA: CPU 0 COR OVER BUSLG Responder RD Memory
MCA: Address 0x216a6f1d0
MCA: Misc 0xc01b0fff01000000
MCA: Bank 4, Status 0xdc544100e0080a13
MCA: Global Cap 0x0000000000000106, Status 0x0000000000000000
MCA: Vendor "AuthenticAMD", ID 0x100f43, APIC ID 0
MCA: CPU 0 COR OVER BUSLG Responder RD Memory
MCA: Address 0x216be3040
MCA: Misc 0xc01b0fff01000000
MCA: Bank 4, Status 0xdc544100e0080a13
MCA: Global Cap 0x0000000000000106, Status 0x0000000000000000
MCA: Vendor "AuthenticAMD", ID 0x100f43, APIC ID 0
MCA: CPU 0 COR OVER BUSLG Responder RD Memory
MCA: Address 0x217b3c720
MCA: Misc 0xc01a0ffb01000000

The first two were triggered by the interrupt, the last one is
from the periodic polling. Note the values in Misc.

[jhb]

Aside from the comment about resume, I think this looks fine.

sys/x86/x86/mca.c

1005 ↗

(On Diff #25217)

I think this should be the lapic's job, but you need to ensure that lapic_resume() will DTRT. I think that's something to be fixed in the other review that added the lapic EVLT support.

For the normal LVT entries we keep an lvt[] array in each software lapic structure. I think you should do the same with having an evlt[] array with relevant fields and have the enable_mca_lvt bit modify the elvt[] array and rely on lapic_setup() to actually program the ELVTs. That will then handle resume correctly.

[jhb]

[avg]

rebase

[avg]

enhance amd mce thresholding

• better name for MC_MISC_AMDNB_OVERFLOW, no need to save one character
• don't worry about lapic configuration on resume, it's handled by lapic itself
• extract common code shared between initial setup and resume