riscv, pmap: extend the set of TLB management functions

[mhorne]

Summary

The RISC-V privilege specification describes the various combinations of
uses for the svence.vma instruction. Depending on the arguments of rs1
and rs2, it can be used in one of four ways:

1. Invalidate the entire local TLB, including global mappings (rs1 == x0, rs2 == x0).
2. Invalidate all non-global mappings for a particular address space (rs1 == x0, rs2 != x0).
3. Invalidate a single page (rs1 != x0, rs2 == x0).
4. Invalidate a non-global page in a particular address space (rs1 != x0, rs2 != x0).

We have primitives for each of these cases, defined in cpufunc.h.

This patch is the foundation for two immediate subsequent changes:

• SiFive FU740 sfence.vma errata handling
• PTE 'G'/Global bit

Both of these require some reworking of our PMAP TLB invalidation
functions, which wrap the sfence primitives.

Augment the pmap_invalidate_*() functions to treat kernel mappings
distinctly; perform a global flush in these cases, but in the other/user
pmap cases, use the _asid/non-global sfence variants, with an asid value
of zero.

Introduce another helper function, pmap_local_invalidate_all(), wrapping
sfence_vma() and flushing only the local hart. Replace a few bare
invocations of sfence_vma() with this.

Tweak the function signature of sfence_vma_page_asid() and add some
commentary to the primitives in cpufunc.h.

Finally, this change may also serve well as a foundation for full ASID
support, if this is desired in the future.