clk: Initial support for the SpacemiT K1 clock control units

[bnovkov]

Summary

This change implements the core clknode methods for the SpacemiT K1
clock control units. These methods were used to implement drivers
for the APMU and PLL CCUs. The initial driver for the APMU CCU
only contains clock definitions for the SDHCI controller for now.

Test Plan

Tested on a Banana Pi BPI-F3 board, the PLL and APMU drivers successfully attach. The latter is also used in D57178 to control the SDHCI clocks.
Relevant bootverbose log output:

[[snip]]
k1_pll0: <SpacemiT K1 PLL Clock Control Unit> mem 0xd4090000-0xd4090fff on simplebus0
Clock: pll1, parent: none, freq: 2457600000
Clock: pll2, parent: none, freq: 3000000000
Clock: pll3, parent: none, freq: 3200000000
Clock: pll1_d2, parent: pll1(0), freq: 1228800000
Clock: pll1_d3, parent: pll1(0), freq: 819200000
Clock: pll1_d4, parent: pll1(0), freq: 614400000
Clock: pll1_d5, parent: pll1(0), freq: 491520000
Clock: pll1_d6, parent: pll1(0), freq: 409600000
Clock: pll1_d7, parent: pll1(0), freq: 351085714
Clock: pll1_d8, parent: pll1(0), freq: 307200000
Clock: pll1_d11, parent: pll1(0), freq: 223418181
Clock: pll1_d13, parent: pll1(0), freq: 189046153
Clock: pll1_d23, parent: pll1(0), freq: 106852173
Clock: pll1_d64, parent: pll1(0), freq: 38400000
Clock: pll1_d10_aud, parent: pll1(0), freq: 245760000
Clock: pll1_d100_aud, parent: pll1(0), freq: 24576000
Clock: pll2_d2, parent: pll2(0), freq: 1500000000
Clock: pll2_d3, parent: pll2(0), freq: 1000000000
Clock: pll2_d4, parent: pll2(0), freq: 750000000
Clock: pll2_d5, parent: pll2(0), freq: 600000000
Clock: pll2_d6, parent: pll2(0), freq: 500000000
Clock: pll2_d7, parent: pll2(0), freq: 428571428
Clock: pll2_d8, parent: pll2(0), freq: 375000000
Clock: pll3_d2, parent: pll3(0), freq: 1600000000
Clock: pll3_d3, parent: pll3(0), freq: 1066666666
Clock: pll3_d4, parent: pll3(0), freq: 800000000
Clock: pll3_d5, parent: pll3(0), freq: 640000000
Clock: pll3_d6, parent: pll3(0), freq: 533333333
Clock: pll3_d7, parent: pll3(0), freq: 457142857
Clock: pll3_d8, parent: pll3(0), freq: 400000000
Clock: pll3_80, parent: pll3_d8(0), freq: 20000000
Clock: pll3_40, parent: pll3_d8(0), freq: 40000000
Clock: pll3_20, parent: pll3_d8(0), freq: 80000000
[[snip]]
k1_apmu0: <SpacemitT K1 APMU Clock Controller> mem 0xd4282800-0xd4282bff on simplebus0
Clock: pmua_aclk, parent: pll1_d10_aud(0), freq: 245760000
Clock: sdh_axi_aclk, parent: pmua_aclk(0), freq: 245760000
Clock: sdh0_clk, parent: pll1_d6(0), freq: 409600000
Clock: sdh1_clk, parent: pll1_d6(0), freq: 409600000
Clock: sdh2_clk, parent: pll2_d8(2), freq: 375000000