Add support for more than 2 perf counters into hwpmc_mips(4)

[sobomax]

Summary

o Beef up hwpmc_mips(4) to support more than 2 performance counters on contemporary MIPSes (i.e. 74K and up);

o automatically probe and detect the number of supported counters;

o cleanup and diambiguate access to the PerfCntN and PerfCtlN registers.

[sobomax]

Use consistent names for the control register access macros and functions.