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Add support for more than 2 perf counters into hwpmc_mips(4)
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Authored by sobomax on Mar 15 2016, 4:09 AM.
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o Beef up hwpmc_mips(4) to support more than 2 performance counters on contemporary MIPSes (i.e. 74K and up);

o automatically probe and detect the number of supported counters;

o cleanup and diambiguate access to the PerfCntN and PerfCtlN registers.

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sobomax retitled this revision from to Add support for more than 2 perf counters into hwpmc_mips(4).
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Use consistent names for the control register access macros and functions.