clk/broadcom: Add PLL and PLL channel clock nodes

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Summary

Add bcm_clk_pll and bcm_clk_pll_channel clknodes, and wire them into
the CPRMAN attach path.

bcm_clk_pll manages the A2W PLL hardware:

• set_gate sequences power-up (clear PWRDN, clear ANARST, wait for FLOCK with timeout, set PRST_DISABLE) and power-down in reverse
• recalc_freq computes Fout = Fosc * (ndiv + frac/frac_denom) / pdiv using integer arithmetic scaled by frac_denom to avoid floating point
• set_freq solves for ndiv+frac given a target frequency, clamping to the hardware field widths and honouring CLK_SET_ROUND_UP/DOWN
• The a2w_xosc_ctrl enable bit is set on power-up when present

bcm_clk_pll_channel manages the per-output divider:

• gate logic corrected: clearing disable bit enables the output
• min_div fixed to 1 (was erroneously set to 1 << div_width)
• cm_offset, hold_shift, load_shift now initialised from clkdef
• Function names aligned to bcm_clk_pll_channel_* prefix
• BSD-2-Clause licence header added to .c and .h

bcm_cprman_clk_data gains pll_clks and pll_chan_clks arrays;
bcm_cprman_attach registers PLLs and channels before peripheral clocks.

Signed-off-by: perdixky <[e-mail]>

[mhorne]

Similar comments to D55907. The structure looks good, but I did not review the clock method logic.

sys/dev/clk/broadcom/bcm_clk_pll.h

39–41

At least some of the fields defined in this header are not used.

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Updating D55908: clk/broadcom: Add PLL and PLL channel clock nodes

[3293789706_qq.com]

Updating D55908: clk/broadcom: Add PLL and PLL channel clock nodes

[3293789706_qq.com]

Updating D55908: clk/broadcom: Add PLL and PLL channel clock nodes