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ixl(4): Fix errors in queue interrupt setup in MSIX mode.
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Authored by erj on Feb 5 2016, 11:00 PM.

Details

Summary

One of the registers should be cleared instead of writing
the queue index to it, and the queue linked list for each
vector should only include the queue pair's Rx and Tx queues,
not every single other queue's Tx and Rx pairs.

Diff Detail

Repository
rS FreeBSD src repository
Lint
Lint OK
Unit
No Unit Test Coverage
Build Status
Buildable 2405
Build 2421: arc lint + arc unit

Event Timeline

erj updated this revision to Diff 13072.Feb 5 2016, 11:00 PM
erj retitled this revision from to ixl(4): Fix errors in queue interrupt setup in MSIX mode..
erj updated this object.
sbruno accepted this revision.Feb 8 2016, 4:34 PM
sbruno added a reviewer: sbruno.
This revision is now accepted and ready to land.Feb 8 2016, 4:34 PM
jeffrey.e.pieper_intel.com edited edge metadata.

Tested with MSIX queues ranging from 8 to 72.

This revision was automatically updated to reflect the committed changes.