subr_intr: Support per-CPU IPI vectors

[andrew]

Summary

The Arm GICv5 replaces a single software generated interrupt that is
identical on each CPU with an instruction that can raise a specified
Shared Peripheral Interrupt (SPI) or Logical Peripheral Interrupt
(LPI).

As these interrupts will only target a single CPU we will need to
support sending multiple IPIs when targeting multiple CPUs. As such
we need an intr_irqsrc for each CPU/IPI pair.

Add support for this to the common code so other drivers can make use
of this support if needed.

Sponsored by: Arm Ltd

[jrtc27]

This may be a stupid question as I've not reminded myself of the details of INTRng and IPIs, but why can't the PIC expose a single isrc that internally happens to send multiple interrupts as far as the hardware is concerned?

[mmel]

In D51330#1172388, @jrtc27 wrote:

but why can't the PIC expose a single isrc that internally happens to send multiple interrupts as far as the hardware is concerned?

Exactly, unless you want to have per CPU specific vectors for the same SPI/LPI. But that sounds too crazy to be true.