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Differential D50726

arm64: Add more CPU MIDR values
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Authored by andrew on Jun 6 2025, 5:21 PM.
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bcran
emaste
imp

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manu
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arm64
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rG61d0cea4c00f: arm64: Workaround the following errata
rG935f00c4ddf6: arm64: Add more CPU MIDR values
rG124b5dbf5c09: arm64: Add more CPU MIDR values
Summary

Found in Linux and https://github.com/arm-software/data

Sponsored by: Arm Ltd

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rG FreeBSD src repository
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Event Timeline

andrew created this revision.Jun 6 2025, 5:21 PM
Herald added a reviewer: manu. · View Herald TranscriptJun 6 2025, 5:21 PM
Herald added subscribers: emaste, imp. · View Herald Transcript
andrew requested review of this revision.Jun 6 2025, 5:21 PM
Harbormaster completed remote builds in B64685: Diff 156646.Jun 6 2025, 5:21 PM
bcran added a subscriber: bcran.Jun 6 2025, 8:57 PM
bcran added inline comments.
sys/arm64/arm64/identcpu.c
262

To be consistent, "AmpereOne" should probably be "AmpereOne AC03", and "AmpereOne-1A" should be "AmpereOne AC04".
There will also be an "AmpereOne AC04_1".

For example, see https://amperecomputing.com/tutorials/gcc-guide-ampere-processors.

andrew added inline comments.Jun 9 2025, 9:07 AM
sys/arm64/arm64/identcpu.c
262

Is AC04_1 the 0xac5 case I see in LLVM?

andrew added inline comments.Jun 10 2025, 9:52 AM
sys/arm64/arm64/identcpu.c
262

Based on the errata doc I found it looks like the AC04 and AC04_1 have the same midr so will both show up as the former.

andrew updated this revision to Diff 156776.Jun 10 2025, 9:54 AM

Update the AmpereOne names

Harbormaster completed remote builds in B64740: Diff 156776.Jun 10 2025, 9:54 AM
This revision was not accepted when it landed; it landed in state Needs Review.Jun 23 2025, 1:20 PM
Closed by commit rG124b5dbf5c09: arm64: Add more CPU MIDR values (authored by andrew). · Explain Why
This revision was automatically updated to reflect the committed changes.
andrew added a commit: rG124b5dbf5c09: arm64: Add more CPU MIDR values.
andrew added a commit: rG935f00c4ddf6: arm64: Add more CPU MIDR values.Jan 15 2026, 2:51 PM
markj added a commit: rG61d0cea4c00f: arm64: Workaround the following errata.Tue, Jun 9, 7:19 PM

Revision Contents
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sys/
arm64/
arm64/
28 lines
include/
20 lines

Diff 157453

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sys/arm64/arm64/identcpu.c

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sys/arm64/include/cpu.h

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