hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bit
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Authored by andrew on May 20 2025, 10:42 AM.

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arm64
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rG48d41181ee1d: hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bit

Summary

It may return data in the upper 32-bits when FEAT_PMUv3p5 is
implemented so mask those bits off.

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rG FreeBSD src repository

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Event Timeline

andrew created this revision.May 20 2025, 10:42 AM

Herald added a reviewer: gnn. · View Herald TranscriptMay 20 2025, 10:42 AM

Herald added subscribers: emaste, imp. · View Herald Transcript

andrew requested review of this revision.May 20 2025, 10:42 AM

Harbormaster completed remote builds in B64311: Diff 155740.May 20 2025, 10:42 AM

andrew added a parent revision: D50430: arm64: Add more PMCR_EL0 fields.May 20 2025, 10:42 AM

andrew added a child revision: D50432: hwpmc/arm64: The counter is 64-bit.

This revision was not accepted when it landed; it landed in state Needs Review.May 28 2025, 1:35 PM

Closed by commit rG48d41181ee1d: hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bit (authored by andrew). · Explain Why

This revision was automatically updated to reflect the committed changes.

andrew added a commit: rG48d41181ee1d: hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bit.

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sys/

dev/

hwpmc/

hwpmc_arm64.c

6 lines

Diff 156183

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sys/dev/hwpmc/hwpmc_arm64.c

hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bitClosedPublicActions