hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bit
It may return data in the upper 32-bits when FEAT_PMUv3p5 is
implemented so mask those bits off.
Sponsored by: Arm Ltd
Differential Revision: https://reviews.freebsd.org/D50431
Description
Description
Details
Details
- Provenance
andrew Authored on May 27 2025, 7:55 PM - Differential Revision
- D50431: hwpmc/arm64: The PMXEVCNTR_EL0 register is 64-bit
- Parents
- rG33ec71d6c0e9: arm64: Add more PMCR_EL0 fields
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