arm64: tidy up and enable top-byte-ignore (TBI) in the kernel

[harry.moulton_arm.com]

Summary

TBI is a default feature of ARMv8.0, allowing for the top byte of a
virtual address to be ignored by hardware during address translation and
is a prerequisite for features such as Memory Tagging Extension (MTE)

In order for TBI to be enabled in the kernel, various places that handle
userspace addresses need to be updated to handle TBI, particularly where
an address is compared against the VM_MAXUSER_ADDRESS, as currently
these checks fail if the top byte of a userspace address is set.

TBI has two options to be enabled, via the TCR_EL1 system register. TBI1
will enable it for kernel space, and TBI0 for user space. TBI will only
be enabled for user space for the time being.

Sponsored-by: Arm Ltd
Signed-off-by: Harry Moulton <[e-mail]>

[andrew]

sys/arm64/arm64/copyinout.S

35

Why is this needed?

sys/arm64/arm64/locore.S

948–949

I think we should wait before enabling this as we need to handle data aborts with a non-zero top byte, and decide if enabling TBI is an ABI change or not.

[kib]

At least for Intel, enabling LAM is the ABI change. I believe all our tier-1 platforms must be measured by the same standard.