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riscv timer: use stimecmp CSR when available

Authored by mhorne on Tue, May 23, 5:16 PM.
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The Sstc extension defines a new stimecmp CSR, allowing supervisor
software to set the timer, rather than just read it. When supported,
using this avoids the frequent trips through the SBI every time the
CPU's timer expires.

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This revision is now accepted and ready to land.Tue, May 23, 9:03 PM

Thanks for adding this - I was recently trying to debug RISC-V issues using qemu tracing and the constant SBI calls meant that it made essentially zero progress since tracing slowed down qemu so much that the next timer interrupt fired once it returned from the sbi call.

This revision was automatically updated to reflect the committed changes.