Pondicherry2 memory controller (ECC) driver

[stevek]

Summary

Address decoding implemented by reading MCH registers to get the
mapping bet ween address bits and physical location in RAM

Decoding has two stages:

1. Convert physical address to PMI.
2. Convert PMI to location in DRAM.

Only single channel and slice memory configuration.

Correctable errors:
Process a CMC(correctable machine check) by decoding the faulty
address and printing its location in DRAM (bank,rank etc.) to
the console.

Uncorrectable errors:
If the board was rebooted due to an UCE log that in dmesg.

Device sysctls:

1. Read correctable ECC error count: sysctl dev.pnd2_edac.0.ce_count
2. Enable/Disable patrol scrub: sysctl dev.pnd2_edac.0.patrol_scrub=1/0

Errors are injected by writing to a newly created sysctl, 2 for
UCE and 1 for CE.

Note: the error injection feature must be enabled in firmware.

Usage:

1. Inject uncorrectable ECC error: sysctl dev.pnd2_edac.0.err_inject=1
2. Inject correctable ECC error: sysctl dev.pnd2_edac.0.err_inject=2

Note: error injection feature must be enabled in BIOS by enabling
"Security relaxation".

Submitted by: Lakshman Likith Nudurupati <[e-mail]>
Sponsored by: Juniper Networks, Inc.
Obtained from: Semihalf

[stevek]

Accidentally created